Sciences & Société
Soutenance de thèse : Yue MA
First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits
Doctorant : Yue MA
Laboratoire INSA : INL
Ecole doctorale : ED160 E.E.A
Three Dimensional (3D) Integration and Packaging has been successful in mainstream devices to increase logic density and to reduce data movement distances. It solves the fundamental limits of scaling e.g. increasing delay in interconnections, development costs and variability. Most memory devices shipped today have some form of chip-stacking involved. But because of the power dissipation limits of ICs, today’s MPU’s operating frequency has been limited to a few GHz.
The aim of the thesis is to provide a global design method for the 3D integrated circuit in electrical, thermal, electro-thermal and also noise field. To this end, the research question is as follows: How to realize the 3D IC design, how to manage VLS 3D IC and how to solve the thermal issues in the 3D IC. In this context, the simulation methods for substrate and also relative connectivity (TSV, RDL, Micro strip and circuits embedded into the substrate) are proposed.
In order to satisfy the research demand, a 3D-TLE and a substrate impedance are programmed in Matlab, which can automatically extract from any contacts; impedance, of arbitrary shape and arbitrary material. The extractor is 100% compatible with SPICE core simulator, and verified with measurement results and FEM simulation results. And as for a demo, a 25 GHz frequency and 2GHz bandwidth RF filter is propose in this work. Another electro-thermal simulator is also programmed and verified with ADS. As a solution to the local heat dissipation, flat heat pipe (FHP) is proposed as a prospective component. The heat-pipe model is verified with FEM simulation. The substrates noise analysis method and electrical and thermos-mechanical keep-out-of-zone (KOZ) calculation methods are also presented.
Amphithéâtre P.G. de Gennes (Villeurbanne)