06 avr
06/04/2017 14:00


Soutenance de thèse : Matei Valentin ISTOAN

High-performance coarse operators for FPGA-based computing

Doctorant : Matei Valentin ISTOAN

Laboratoire INSA : CITI Lab
Ecole doctorale : Informatique Et Mathématiques de Lyon

Field-Programmable Gate Arrays (FPGAs) have been shown to outperform usual microprocessors. The circuit paradigm enables implementing parallel computational on the device, data flowing from a producing task to a receiving task efficiently. FPGAs also enable arithmetic efficiency: every bit computed is useful to the final result. Microprocessors have for most numerical applications a poor efficiency. FPGA arithmetic shouldn’t rely on operators imitating processors. In principle, there is no fixed instruction in FPGAs: application-specific operators are explored and are radically different from those of microprocessors.

The thesis focuses on coarser computing cores, in three main directions:

1/ FPGA computing needs an equivalent of the standard mathematical library (functions such as exponential, logarithm or trigonometric functions). A goal is the investigation of FPGA-specific approaches for such functions. Each function should be as versatile and flexible as possible. Arithmetic efficiency requires error analysis and parameter tuning, and a fine understanding of the algorithms used. A goal is to provide an open- ended library, where functions are described as high-level objects such as mathematical expressions.

2/ Digital filters are a useful family of coarse operators resembling elementary functions: they can be specified at a high level as a transfer function with constraints on the signal/noise ratio, and their implementation (FIR, IIR) is an arithmetic datapath based on addition and multiplication. The main goal is to transform a high-level specification into a filter in an automated way.

3/ For coarse operators to achieve maximum performance efficient pipelining is required. The context of an arithmetic datapath provides knowledge that could be exploited to assist these steps within the FloPoCo framework.

It is currently still difficult to configure an FPGA as a circuit implementing some functionality. By providing high-quality of-the-shelf operators for coarse computing cores, the goal is to make FPGA-based computing practical.