Sciences & Société
Soutenance de thèse en visioconférence : Andrea BOCCO
A variable precision hardware acceleration for scientific computing
Doctorant : Andrea BOCCO
Laboratoire INSA : CITI
Ecole doctorale : ED512 : Informatique et Mathématiques de Lyon
Most of the Floating-Point (FP) hardware units support the formats specified in the IEEE 754 standard. These formats have fixed bit-lengths. Some applications, for instance linear system solvers, take benefit of different FP formats with different sizes and different tradeoffs among the exponent and the mantissa fields. Variable Precision (VP) formats can cover these needs. We propose a VP FP computing system based on three computation layers. The external one which supports legacy IEEE formats for input and output variables. The internal one which uses variable length internal registers for inner loop multiply-add. And an intermediate one which supports loads and stores of intermediate results without loosing precision, with a dynamically adjustable VP format. The VP unit uses the UNUM type I as memory format, proposing solutions to address some of its pitfalls. The unit supports up to 512 bits of precision, internally and in memory, for both interval and scalar computing. The user can configure the storage format up to 8-bit granularity, and the internal computing precision at 64-bit granularity. This work is integrated on FPGA. Compared with the MPFR software library, the proposed unit achieves speedups between 3.5x and 18x, with comparable accuracy. Experiments emulated in FPGA show that the latency and the computation accuracy of this system scale linearly with the memory format length set by the user. The high accuracy achieved by our unit opens the possibility to use direct methods, which are more sensible to computational error, instead of iterative methods, which always converge but their latency is 10 times higher than direct ones. In iterative methods, the usage of VP formats helps to drastically reduce the number of iterations required by the iterative algorithm to converge, reducing the application latency of up to 50%.